From de1f0e798b0102abb1d780a23e2ac7a4cef8523d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 18 Apr 2016 16:50:15 +0000 Subject: [PATCH 12/15] arch/arm/mach-rockchip/rk3288/sdram_rk3288: Fix incorrect SDRAM size detection Also add debug statements Signed-off-by: Timothy Pearson --- arch/arm/mach-rockchip/rk3288/sdram_rk3288.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c index 17daeca..c7dddad 100644 --- a/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c +++ b/arch/arm/mach-rockchip/rk3288/sdram_rk3288.c @@ -1,4 +1,5 @@ /* + * (C) Copyright 2016 Raptor Engineering, LLC * (C) Copyright 2015 Google, Inc * Copyright 2014 Rockchip Inc. * @@ -592,7 +593,8 @@ static int sdram_init(const struct dram_info *dram, return -E2BIG; } - debug("ddr clk %s\n", dram->ddr_clk->name); + debug("DRAM type: %d\n", sdram_params->base.dramtype); + debug("DDR clock: %s\n", dram->ddr_clk->name); ret = clk_set_rate(dram->ddr_clk, sdram_params->base.ddr_freq); debug("ret=%d\n", ret); if (ret) { @@ -686,7 +688,7 @@ static int sdram_init(const struct dram_info *dram, ddr_phy_ctl_reset(dram->cru, channel, 0); udelay(10); } - debug("failed!"); + debug("training failed!"); return -EIO; } @@ -725,7 +727,7 @@ size_t sdram_size_mb(struct rk3288_pmu *pmu) SYS_REG_CS0_ROW_MASK); cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & SYS_REG_CS1_ROW_MASK); - bw = (2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch)) & + bw = 2 >> (sys_reg >> SYS_REG_BW_SHIFT(ch) & SYS_REG_BW_MASK); row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & SYS_REG_ROW_3_4_MASK; -- 1.9.1