From b41212811f39bde332d0c0d57711d0278288dc00 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 18 Apr 2016 16:48:04 +0000 Subject: [PATCH 09/15] arm/cpu/armv7/nonsec_virt: Initialize non-secure TTBCR Signed-off-by: Timothy Pearson --- arch/arm/cpu/armv7/nonsec_virt.S | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index b7563ed..bab6581 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -68,6 +68,7 @@ _secure_monitor: #endif mrc p15, 0, r5, c1, c1, 0 @ read SCR + mrc p15, 0, r7, c2, c0, 2 @ read secure TTBCR bic r5, r5, #0x4a @ clear IRQ, EA, nET bits orr r5, r5, #0x31 @ enable NS, AW, FW bits @ FIQ preserved for secure mode @@ -88,6 +89,7 @@ _secure_monitor: ands r4, r4, #CPUID_ARM_GENTIMER_MASK @ test arch timer bits movne r4, #0 mcrrne p15, 4, r4, r4, c14 @ Reset CNTVOFF to zero + 1: mov lr, ip mov ip, #(F_BIT | I_BIT | A_BIT) @ Set A, I and F @@ -95,6 +97,12 @@ _secure_monitor: orrne ip, ip, #T_BIT @ Set T if Thumb orr ip, ip, r6 @ Slot target mode in msr spsr_cxfs, ip @ Set full SPSR + + movs r8, r7 @ exit secure mode + isb + + mcr p15, 0, r7, c2, c0, 2 @ Initialize non-secure TTBCR + movs pc, lr @ ERET to non-secure ENTRY(_do_nonsec_entry) -- 1.9.1