From 38de3f7031b2815fb0072e7e6ea554dd5a59c75d Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 18 Apr 2016 16:46:35 +0000 Subject: [PATCH 07/15] arch/arm/cpu/armv7/virt-v7: Add initial TZPC setup stub Also add additional non-secure mode switch debug functions Signed-off-by: Timothy Pearson --- arch/arc/lib/bootm.c | 1 + arch/arm/cpu/armv7/virt-v7.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/arc/lib/bootm.c b/arch/arc/lib/bootm.c index 04d9d9c..cb43264 100644 --- a/arch/arc/lib/bootm.c +++ b/arch/arc/lib/bootm.c @@ -84,6 +84,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) } smp_set_core_boot_addr((unsigned long)kernel_entry, -1); + debug("%s: kicking secondary CPUs\n", __func__); smp_kick_all_cpus(); if (!fake) diff --git a/arch/arm/cpu/armv7/virt-v7.c b/arch/arm/cpu/armv7/virt-v7.c index 9c53306..98bc28d 100644 --- a/arch/arm/cpu/armv7/virt-v7.c +++ b/arch/arm/cpu/armv7/virt-v7.c @@ -1,4 +1,5 @@ /* + * (C) 2016 Raptor Engineering, LLC * (C) Copyright 2013 * Andre Przywara, Linaro * @@ -26,6 +27,7 @@ static unsigned int read_id_pfr1(void) static unsigned long get_gicd_base_address(void) { #ifdef CONFIG_ARM_GIC_BASE_ADDRESS + debug("%s: using %08x as GIC base address\n", __func__, CONFIG_ARM_GIC_BASE_ADDRESS); return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; #else unsigned periphbase; @@ -42,6 +44,8 @@ static unsigned long get_gicd_base_address(void) return -1; } + debug("%s: using %08x as GIC base address\n", __func__, periphbase); + return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; #endif } @@ -73,9 +77,13 @@ void __weak smp_kick_all_cpus(void) { unsigned long gic_dist_addr; + debug("%s (virt-v7)\n", __func__); + gic_dist_addr = get_gicd_base_address(); - if (gic_dist_addr == -1) + if (gic_dist_addr == -1) { + printf("%s: invalid GIC base address\n", __func__); return; + } kick_secondary_cpus_gic(gic_dist_addr); } @@ -84,19 +92,27 @@ __weak void psci_board_init(void) { } +void __weak armv7_nonsec_tzpc_init(void) +{ +} + int armv7_init_nonsec(void) { unsigned int reg; unsigned itlinesnr, i; unsigned long gic_dist_addr; + debug("%s\n", __func__); + /* check whether the CPU supports the security extensions */ reg = read_id_pfr1(); if ((reg & 0xF0) == 0) { - printf("nonsec: Security extensions not implemented.\n"); + printf("%s: Security extensions not implemented (%08x).\n", __func__, reg); return -1; } + armv7_nonsec_tzpc_init(); + /* the SCR register will be set directly in the monitor mode handler, * according to the spec one should not tinker with it in secure state * in SVC mode. Do not try to read it once in non-secure state, @@ -104,8 +120,10 @@ int armv7_init_nonsec(void) */ gic_dist_addr = get_gicd_base_address(); - if (gic_dist_addr == -1) + if (gic_dist_addr == -1) { + printf("%s: invalid GIC base address\n", __func__); return -1; + } /* enable the GIC distributor */ writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, @@ -113,6 +131,7 @@ int armv7_init_nonsec(void) /* TYPER[4:0] contains an encoded number of available interrupts */ itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; + debug("%s: itlinesnr: %d\n", __func__, itlinesnr); /* set all bits in the GIC group registers to one to allow access * from non-secure state. The first 32 interrupts are private per @@ -133,10 +152,16 @@ int armv7_init_nonsec(void) #ifndef CONFIG_ARMV7_PSCI smp_set_core_boot_addr((unsigned long)secure_ram_addr(_smp_pen), -1); + debug("%s: going to kick secondary CPUs\n", __func__); smp_kick_all_cpus(); #endif /* call the non-sec switching code on this CPU also */ + debug("%s: going to switch BSP to non-secure mode\n", __func__); secure_ram_addr(_nonsec_init)(); + debug("%s: done (new BSP ICDISR0: %08x)\n", __func__, readl(gic_dist_addr + GICD_IGROUPRn)); + for (i = 0; i < 32; i += 4) { + debug("%s: ICDIPTR%d: %08x\n", __func__, i, readl(gic_dist_addr + GICD_ITARGETSRn + 4 * i)); + } return 0; } -- 1.9.1