From 11f7f87a0c2c5951e4c06f3b9d9bc7bc61878390 Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 18 Apr 2016 16:44:18 +0000 Subject: [PATCH 06/15] spl: Don't strip aliases or stdout-path from SPL DTB Signed-off-by: Timothy Pearson --- arch/arm/dts/rk3288-speedy-4g.dts | 148 ++++++ arch/arm/dts/rk3288-veyron-ddr3.dtsi | 22 + arch/arm/dts/rk3288-veyron-lpddr-elpida-4g.dtsi | 22 + arch/arm/include/asm/arch-rockchip/tzpc.h | 58 +++ board/google/chromebook_speedy/Kconfig | 15 + board/google/chromebook_speedy/MAINTAINERS | 6 + board/google/chromebook_speedy/Makefile | 7 + board/google/chromebook_speedy/speedy.c | 7 + configs/chromebook_speedy_defconfig | 640 ++++++++++++++++++++++++ include/configs/chromebook_speedy.h | 36 ++ scripts/Makefile.spl | 2 +- 11 files changed, 962 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/rk3288-speedy-4g.dts create mode 100644 arch/arm/dts/rk3288-veyron-ddr3.dtsi create mode 100644 arch/arm/dts/rk3288-veyron-lpddr-elpida-4g.dtsi create mode 100644 arch/arm/include/asm/arch-rockchip/tzpc.h create mode 100644 board/google/chromebook_speedy/Kconfig create mode 100644 board/google/chromebook_speedy/MAINTAINERS create mode 100644 board/google/chromebook_speedy/Makefile create mode 100644 board/google/chromebook_speedy/speedy.c create mode 100644 configs/chromebook_speedy_defconfig create mode 100644 include/configs/chromebook_speedy.h diff --git a/arch/arm/dts/rk3288-speedy-4g.dts b/arch/arm/dts/rk3288-speedy-4g.dts new file mode 100644 index 0000000..db71863 --- /dev/null +++ b/arch/arm/dts/rk3288-speedy-4g.dts @@ -0,0 +1,148 @@ +/* + * Google Veyron Speedy Rev 1+ board device tree source + * + * Copyright 2015 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/dts-v1/; +#include "rk3288-veyron-chromebook.dtsi" +#include "rk3288-veyron-lpddr.dtsi" +#include "cros-ec-sbs.dtsi" + +/ { + model = "Google Speedy"; + compatible = "google,veyron-speedy-rev9", "google,veyron-speedy-rev8", + "google,veyron-speedy-rev7", "google,veyron-speedy-rev6", + "google,veyron-speedy-rev5", "google,veyron-speedy-rev4", + "google,veyron-speedy-rev3", "google,veyron-speedy-rev2", + "google,veyron-speedy", "google,veyron", "rockchip,rk3288"; + + panel_regulator: panel-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_enable_h>; + regulator-name = "panel_regulator"; + vin-supply = <&vcc33_sys>; + }; + + vcc18_lcd: vcc18-lcd { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 13 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&avdd_1v8_disp_en>; + regulator-name = "vcc18_lcd"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc18_wl>; + }; + + backlight_regulator: backlight-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&bl_pwr_en>; + regulator-name = "backlight_regulator"; + vin-supply = <&vcc33_sys>; + startup-delay-us = <15000>; + }; +}; + +&backlight { + power-supply = <&backlight_regulator>; +}; + +&panel { + power-supply= <&panel_regulator>; +}; + +&rk808 { + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>; + dvs-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>, + <&gpio7 15 GPIO_ACTIVE_HIGH>; +}; + +&sdmmc { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio + &sdmmc_bus4>; + disable-wp; +}; + +&thermal { + #include "rk3288-speedy-thermal.dtsi" +}; + +&vcc_5v { + enable-active-high; + gpio = <&gpio7 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&drv_5v>; +}; + +&vcc50_hdmi { + enable-active-high; + gpio = <&gpio5 19 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc50_hdmi_en>; +}; + +&edp { + pinctrl-names = "default"; + pinctrl-0 = <&edp_hpd>; +}; + +&pinctrl { + backlight { + bl_pwr_en: bl_pwr_en { + rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + buck-5v { + drv_5v: drv-5v { + rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + edp { + edp_hpd: edp_hpd { + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>; + }; + }; + + hdmi { + vcc50_hdmi_en: vcc50-hdmi-en { + rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + lcd { + lcd_enable_h: lcd-en { + rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + + avdd_1v8_disp_en: avdd-1v8-disp-en { + rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + dvs_1: dvs-1 { + rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>; + }; + + dvs_2: dvs-2 { + rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + diff --git a/arch/arm/dts/rk3288-veyron-ddr3.dtsi b/arch/arm/dts/rk3288-veyron-ddr3.dtsi new file mode 100644 index 0000000..1866cdf --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-ddr3.dtsi @@ -0,0 +1,22 @@ +/* + * Google Veyron (and derivatives) fragment for ddr3 ddrfreq settings + * + * Copyright 2015 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&dmc { + status = "okay"; + rockchip,pd-enable-freq = <533000000>; + operating-points = < + /* KHz uV */ + 200000 1050000 + 333000 1100000 + 533000 1150000 + 666000 1200000 + >; +}; + diff --git a/arch/arm/dts/rk3288-veyron-lpddr-elpida-4g.dtsi b/arch/arm/dts/rk3288-veyron-lpddr-elpida-4g.dtsi new file mode 100644 index 0000000..be88077 --- /dev/null +++ b/arch/arm/dts/rk3288-veyron-lpddr-elpida-4g.dtsi @@ -0,0 +1,22 @@ +/* + * Google Veyron (and derivatives) fragment for lpddr ddrfreq settings + * + * Copyright 2015 Google, Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +&dmc { + status = "okay"; + rockchip,odt-disable-freq = <666000000>; + rockchip,pd-enable-freq = <333000000>; + operating-points = < + /* KHz uV */ + 200000 1050000 + 333000 1100000 + 533000 1150000 + >; +}; + diff --git a/arch/arm/include/asm/arch-rockchip/tzpc.h b/arch/arm/include/asm/arch-rockchip/tzpc.h new file mode 100644 index 0000000..0a4be23 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/tzpc.h @@ -0,0 +1,58 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __TZPC_H_ +#define __TZPC_H_ + +#ifndef __ASSEMBLY__ +struct exynos_tzpc { + unsigned int r0size; + char res1[0x7FC]; + unsigned int decprot0stat; + unsigned int decprot0set; + unsigned int decprot0clr; + unsigned int decprot1stat; + unsigned int decprot1set; + unsigned int decprot1clr; + unsigned int decprot2stat; + unsigned int decprot2set; + unsigned int decprot2clr; + unsigned int decprot3stat; + unsigned int decprot3set; + unsigned int decprot3clr; + char res2[0x7B0]; + unsigned int periphid0; + unsigned int periphid1; + unsigned int periphid2; + unsigned int periphid3; + unsigned int pcellid0; + unsigned int pcellid1; + unsigned int pcellid2; + unsigned int pcellid3; +}; + +#define EXYNOS4_NR_TZPC_BANKS 6 +#define EXYNOS5_NR_TZPC_BANKS 10 + +/* TZPC : Register Offsets */ +#define TZPC_BASE_OFFSET 0x10000 + +/* + * TZPC Register Value : + * R0SIZE: 0x0 : Size of secured ram + */ +#define R0SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF +void tzpc_init(void); + +#endif + +#endif diff --git a/board/google/chromebook_speedy/Kconfig b/board/google/chromebook_speedy/Kconfig new file mode 100644 index 0000000..7b20a41 --- /dev/null +++ b/board/google/chromebook_speedy/Kconfig @@ -0,0 +1,15 @@ +if TARGET_CHROMEBOOK_SPEEDY + +config SYS_BOARD + default "chromebook_speedy" + +config SYS_VENDOR + default "google" + +config SYS_CONFIG_NAME + default "chromebook_speedy" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/google/chromebook_speedy/MAINTAINERS b/board/google/chromebook_speedy/MAINTAINERS new file mode 100644 index 0000000..c81a288 --- /dev/null +++ b/board/google/chromebook_speedy/MAINTAINERS @@ -0,0 +1,6 @@ +CHROMEBOOK SPEEDY BOARD +M: Timothy Pearson +S: Maintained +F: board/google/chromebook_speedy/ +F: include/configs/chromebook_speedy.h +F: configs/chromebook_speedy_defconfig diff --git a/board/google/chromebook_speedy/Makefile b/board/google/chromebook_speedy/Makefile new file mode 100644 index 0000000..d0b68c7 --- /dev/null +++ b/board/google/chromebook_speedy/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += speedy.o diff --git a/board/google/chromebook_speedy/speedy.c b/board/google/chromebook_speedy/speedy.c new file mode 100644 index 0000000..5119e95 --- /dev/null +++ b/board/google/chromebook_speedy/speedy.c @@ -0,0 +1,7 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig new file mode 100644 index 0000000..4cab2e8 --- /dev/null +++ b/configs/chromebook_speedy_defconfig @@ -0,0 +1,640 @@ +# +# Automatically generated file; DO NOT EDIT. +# U-Boot 2016.03-rc3 Configuration +# +CONFIG_CREATE_ARCH_SYMLINK=y +CONFIG_HAVE_GENERIC_BOARD=y +CONFIG_SYS_GENERIC_BOARD=y +# CONFIG_ARC is not set +CONFIG_ARM=y +# CONFIG_AVR32 is not set +# CONFIG_BLACKFIN is not set +# CONFIG_M68K is not set +# CONFIG_MICROBLAZE is not set +# CONFIG_MIPS is not set +# CONFIG_NDS32 is not set +# CONFIG_NIOS2 is not set +# CONFIG_OPENRISC is not set +# CONFIG_PPC is not set +# CONFIG_SANDBOX is not set +# CONFIG_SH is not set +# CONFIG_SPARC is not set +# CONFIG_X86 is not set +CONFIG_SYS_ARCH="arm" +CONFIG_SYS_CPU="armv7" +CONFIG_SYS_SOC="rockchip" +CONFIG_SYS_VENDOR="google" +CONFIG_SYS_BOARD="chromebook_speedy" +CONFIG_SYS_CONFIG_NAME="chromebook_speedy" + +# +# ARM architecture +# +CONFIG_HAS_VBAR=y +CONFIG_HAS_THUMB2=y +CONFIG_CPU_V7=y +# CONFIG_SEMIHOSTING is not set +# CONFIG_SYS_L2CACHE_OFF is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_TARGET_EDB93XX is not set +# CONFIG_TARGET_VCMA9 is not set +# CONFIG_TARGET_SMDK2410 is not set +# CONFIG_TARGET_ASPENITE is not set +# CONFIG_TARGET_GPLUGD is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_KIRKWOOD is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_TARGET_DEVKIT3250 is not set +# CONFIG_TARGET_WORK_92105 is not set +# CONFIG_TARGET_MX25PDK is not set +# CONFIG_TARGET_ZMX25 is not set +# CONFIG_TARGET_APF27 is not set +# CONFIG_TARGET_APX4DEVKIT is not set +# CONFIG_TARGET_XFI3 is not set +# CONFIG_TARGET_M28EVK is not set +# CONFIG_TARGET_MX23EVK is not set +# CONFIG_TARGET_MX28EVK is not set +# CONFIG_TARGET_MX23_OLINUXINO is not set +# CONFIG_TARGET_BG0900 is not set +# CONFIG_TARGET_SANSA_FUZE_PLUS is not set +# CONFIG_TARGET_SC_SPS_1 is not set +# CONFIG_ORION5X is not set +# CONFIG_TARGET_SPEAR300 is not set +# CONFIG_TARGET_SPEAR310 is not set +# CONFIG_TARGET_SPEAR320 is not set +# CONFIG_TARGET_SPEAR600 is not set +# CONFIG_TARGET_STV0991 is not set +# CONFIG_TARGET_X600 is not set +# CONFIG_TARGET_IMX31_PHYCORE is not set +# CONFIG_TARGET_MX31ADS is not set +# CONFIG_TARGET_MX31PDK is not set +# CONFIG_TARGET_WOODBURN is not set +# CONFIG_TARGET_WOODBURN_SD is not set +# CONFIG_TARGET_FLEA3 is not set +# CONFIG_TARGET_MX35PDK is not set +# CONFIG_ARCH_BCM283X is not set +# CONFIG_TARGET_VEXPRESS_CA15_TC2 is not set +# CONFIG_TARGET_VEXPRESS_CA5X2 is not set +# CONFIG_TARGET_VEXPRESS_CA9X4 is not set +# CONFIG_TARGET_KWB is not set +# CONFIG_TARGET_TSERIES is not set +# CONFIG_TARGET_CM_T335 is not set +# CONFIG_TARGET_PEPPER is not set +# CONFIG_TARGET_AM335X_IGEP0033 is not set +# CONFIG_TARGET_PCM051 is not set +# CONFIG_TARGET_DRACO is not set +# CONFIG_TARGET_THUBAN is not set +# CONFIG_TARGET_RASTABAN is not set +# CONFIG_TARGET_PXM2 is not set +# CONFIG_TARGET_RUT is not set +# CONFIG_TARGET_PENGWYN is not set +# CONFIG_TARGET_AM335X_BALTOS is not set +# CONFIG_TARGET_AM335X_EVM is not set +# CONFIG_TARGET_AM335X_SL50 is not set +# CONFIG_TARGET_AM43XX_EVM is not set +# CONFIG_TARGET_BAV335X is not set +# CONFIG_TARGET_TI814X_EVM is not set +# CONFIG_TARGET_TI816X_EVM is not set +# CONFIG_TARGET_BCM28155_AP is not set +# CONFIG_TARGET_BCMCYGNUS is not set +# CONFIG_TARGET_BCMNSP is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_S5PC1XX is not set +# CONFIG_ARCH_HIGHBANK is not set +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_KEYSTONE is not set +# CONFIG_ARCH_MX7 is not set +# CONFIG_ARCH_MX6 is not set +# CONFIG_ARCH_MX5 is not set +# CONFIG_TARGET_M53EVK is not set +# CONFIG_TARGET_MX51EVK is not set +# CONFIG_TARGET_MX53ARD is not set +# CONFIG_TARGET_MX53EVK is not set +# CONFIG_TARGET_MX53LOCO is not set +# CONFIG_TARGET_MX53SMD is not set +# CONFIG_OMAP34XX is not set +# CONFIG_OMAP44XX is not set +# CONFIG_OMAP54XX is not set +# CONFIG_RMOBILE is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_TARGET_CM_T43 is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_TARGET_TS4800 is not set +# CONFIG_TARGET_VF610TWR is not set +# CONFIG_TARGET_COLIBRI_VF is not set +# CONFIG_TARGET_PCM052 is not set +# CONFIG_ARCH_ZYNQ is not set +# CONFIG_ARCH_ZYNQMP is not set +# CONFIG_TEGRA is not set +# CONFIG_TARGET_VEXPRESS64_AEMV8A is not set +# CONFIG_TARGET_VEXPRESS64_BASE_FVP is not set +# CONFIG_TARGET_VEXPRESS64_BASE_FVP_DRAM is not set +# CONFIG_TARGET_VEXPRESS64_JUNO is not set +# CONFIG_TARGET_LS2080A_EMU is not set +# CONFIG_TARGET_LS2080A_SIMU is not set +# CONFIG_TARGET_LS2080AQDS is not set +# CONFIG_TARGET_LS2080ARDB is not set +# CONFIG_TARGET_HIKEY is not set +# CONFIG_TARGET_LS1021AQDS is not set +# CONFIG_TARGET_LS1021ATWR is not set +# CONFIG_TARGET_LS1043AQDS is not set +# CONFIG_TARGET_LS1043ARDB is not set +# CONFIG_TARGET_H2200 is not set +# CONFIG_TARGET_COLIBRI_PXA270 is not set +# CONFIG_ARCH_UNIPHIER is not set +# CONFIG_STM32 is not set +CONFIG_ARCH_ROCKCHIP=y +# CONFIG_TARGET_THUNDERX_88XX is not set +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ROCKCHIP_RK3288=y +# CONFIG_ROCKCHIP_RK3036 is not set +CONFIG_SYS_MALLOC_F=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_DM=y +CONFIG_DM_SERIAL=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DM_I2C=y +CONFIG_DM_GPIO=y +# CONFIG_TARGET_FIREFLY_RK3288 is not set +# CONFIG_TARGET_CHROMEBOOK_JERRY is not set +CONFIG_TARGET_CHROMEBOOK_SPEEDY=y +# CONFIG_TARGET_ROCK2 is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_CPU_V7_HAS_NONSEC=y +CONFIG_CPU_V7_HAS_VIRT=y +CONFIG_ARMV7_NONSEC=y +CONFIG_ARMV7_BOOT_SEC_DEFAULT=y +CONFIG_ARMV7_VIRT=y +CONFIG_SPL_STACK_R_ADDR=0x80000 + +# +# ARM debug +# +# CONFIG_DEBUG_LL is not set +CONFIG_DM_KEYBOARD=y +CONFIG_DEFAULT_DEVICE_TREE="rk3288-speedy-4g" +# CONFIG_I8042_KEYB is not set + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_EXPERT=y +CONFIG_SYS_MALLOC_CLEAR_ON_INIT=y + +# +# Boot images +# +CONFIG_SUPPORT_SPL=y +CONFIG_SPL=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 +# CONFIG_SPL_SEPARATE_BSS is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_FIT_SIGNATURE=y +CONFIG_SYS_EXTRA_OPTIONS="" + +# +# Boot timing +# +# CONFIG_BOOTSTAGE is not set +CONFIG_BOOTSTAGE_USER_COUNT=20 +CONFIG_BOOTSTAGE_STASH_ADDR=0 +CONFIG_BOOTSTAGE_STASH_SIZE=4096 +# CONFIG_CONSOLE_RECORD is not set + +# +# Command line interface +# +# CONFIG_HUSH_PARSER is not set +CONFIG_SYS_PROMPT="=> " + +# +# Autoboot options +# +# CONFIG_AUTOBOOT_KEYED is not set + +# +# Commands +# + +# +# Info commands +# +CONFIG_CMD_BDI=y +CONFIG_CMD_CONSOLE=y +# CONFIG_CMD_CPU is not set +# CONFIG_CMD_LICENSE is not set + +# +# Boot commands +# +CONFIG_CMD_BOOTD=y +CONFIG_CMD_BOOTM=y +CONFIG_CMD_ELF=y +CONFIG_CMD_GO=y +CONFIG_CMD_RUN=y +CONFIG_CMD_IMI=y +# CONFIG_CMD_IMLS is not set +CONFIG_CMD_XIMG=y + +# +# Environment commands +# +CONFIG_CMD_EXPORTENV=y +CONFIG_CMD_IMPORTENV=y +CONFIG_CMD_EDITENV=y +CONFIG_CMD_SAVEENV=y +CONFIG_CMD_ENV_EXISTS=y + +# +# Memory commands +# +CONFIG_CMD_MEMORY=y +CONFIG_CMD_CRC32=y +# CONFIG_LOOPW is not set +# CONFIG_CMD_MEMTEST is not set +# CONFIG_CMD_MX_CYCLIC is not set +# CONFIG_CMD_MEMINFO is not set + +# +# Device access commands +# +CONFIG_CMD_DM=y +# CONFIG_CMD_DEMO is not set +CONFIG_CMD_LOADB=y +CONFIG_CMD_LOADS=y +CONFIG_CMD_FLASH=y +# CONFIG_CMD_NAND is not set +# CONFIG_CMD_SF is not set +# CONFIG_CMD_SPI is not set +# CONFIG_CMD_I2C is not set +# CONFIG_CMD_USB is not set +CONFIG_CMD_FPGA=y +# CONFIG_CMD_GPIO is not set + +# +# Shell scripting commands +# +CONFIG_CMD_ECHO=y +CONFIG_CMD_ITEST=y +CONFIG_CMD_SOURCE=y +# CONFIG_CMD_SETEXPR is not set + +# +# Network commands +# +CONFIG_CMD_NET=y +# CONFIG_CMD_TFTPPUT is not set +# CONFIG_CMD_TFTPSRV is not set +# CONFIG_CMD_RARP is not set +# CONFIG_CMD_DHCP is not set +CONFIG_CMD_NFS=y +# CONFIG_CMD_PING is not set +# CONFIG_CMD_CDP is not set +# CONFIG_CMD_SNTP is not set +# CONFIG_CMD_DNS is not set +# CONFIG_CMD_LINK_LOCAL is not set + +# +# Misc commands +# +# CONFIG_CMD_TIME is not set +CONFIG_CMD_MISC=y +# CONFIG_CMD_TIMER is not set + +# +# Power commands +# +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y + +# +# Security commands +# +CONFIG_SUPPORT_OF_CONTROL=y + +# +# Device Tree Control +# +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +# CONFIG_OF_EMBED is not set +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-1 pinctrl-names clock-names interrupts interrupt-parent interrupt-controller dmas dma-names i2c-scl-falling-time-ns i2c-scl-rising-time-ns dvs-gpios wakeup-source status linux,phandle phandle" +CONFIG_NET=y +# CONFIG_NET_RANDOM_ETHADDR is not set +# CONFIG_NETCONSOLE is not set +CONFIG_NET_TFTP_VARS=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_DM=y +CONFIG_DM_WARN=y +CONFIG_DM_DEVICE_REMOVE=y +CONFIG_DM_STDIO=y +CONFIG_DM_SEQ_ALIAS=y +# CONFIG_SPL_DM_SEQ_ALIAS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_DEVRES is not set +CONFIG_SIMPLE_BUS=y +# CONFIG_SPL_SIMPLE_BUS is not set +CONFIG_OF_TRANSLATE=y +# CONFIG_SPL_OF_TRANSLATE is not set +# CONFIG_ADC is not set +# CONFIG_ADC_EXYNOS is not set +# CONFIG_ADC_SANDBOX is not set +CONFIG_DISK=y + +# +# Clock +# +CONFIG_CLK=y +CONFIG_SPL_CLK=y +# CONFIG_CPU is not set + +# +# Hardware crypto devices +# +# CONFIG_FSL_CAAM is not set + +# +# Demo for driver model +# +# CONFIG_DM_DEMO is not set + +# +# DFU support +# +# CONFIG_DFU_TFTP is not set + +# +# DMA Support +# +# CONFIG_DMA is not set +# CONFIG_TI_EDMA3 is not set + +# +# GPIO Support +# +# CONFIG_ALTERA_PIO is not set +# CONFIG_DWAPB_GPIO is not set +# CONFIG_ATMEL_PIO4 is not set +# CONFIG_LPC32XX_GPIO is not set +CONFIG_ROCKCHIP_GPIO=y +# CONFIG_VYBRID_GPIO is not set + +# +# I2C support +# +# CONFIG_DM_I2C_COMPAT is not set +CONFIG_I2C_CROS_EC_TUNNEL=y +# CONFIG_I2C_CROS_EC_LDO is not set +# CONFIG_DM_I2C_GPIO is not set +# CONFIG_SYS_I2C_INTEL is not set +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +# CONFIG_SPL_I2C_MUX is not set +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_CROS_EC_KEYB=y + +# +# LED Support +# +# CONFIG_LED is not set +# CONFIG_SPL_LED is not set + +# +# Multifunction device drivers +# +# CONFIG_MISC is not set +CONFIG_CMD_CROS_EC=y +CONFIG_CROS_EC=y +# CONFIG_CROS_EC_I2C is not set +# CONFIG_CROS_EC_LPC is not set +CONFIG_CROS_EC_SPI=y +# CONFIG_FSL_SEC_MON is not set +# CONFIG_MXC_OCOTP is not set +CONFIG_PWRSEQ=y +# CONFIG_SPL_PWRSEQ is not set +# CONFIG_PCA9551_LED is not set +CONFIG_RESET=y +# CONFIG_WINBOND_W83627 is not set + +# +# MMC Host controller Support +# +CONFIG_DM_MMC=y +CONFIG_ROCKCHIP_DWMMC=y +# CONFIG_ZYNQ_SDHCI is not set + +# +# MTD Support +# +# CONFIG_MTD is not set + +# +# NAND Device Support +# +# CONFIG_NAND_DENALI is not set +# CONFIG_NAND_VF610_NFC is not set +# CONFIG_NAND_PXA3XX is not set +# CONFIG_NAND_ARASAN is not set + +# +# Generic NAND options +# +# CONFIG_SPL_NAND_DENALI is not set + +# +# SPI Flash Support +# +# CONFIG_SPI_FLASH is not set +# CONFIG_DM_ETH is not set +# CONFIG_PHYLIB is not set +# CONFIG_NETDEVICES is not set + +# +# PCI +# +# CONFIG_DM_PCI is not set + +# +# Pin controllers +# +CONFIG_PINCTRL=y +CONFIG_PINCTRL_FULL=y +CONFIG_PINCTRL_GENERIC=y +CONFIG_PINMUX=y +# CONFIG_PINCONF is not set +CONFIG_SPL_PINCTRL=y +# CONFIG_SPL_PINCTRL_FULL is not set +CONFIG_ROCKCHIP_PINCTRL=y +# CONFIG_ROCKCHIP_3036_PINCTRL is not set + +# +# Power +# +CONFIG_DM_PMIC=y +CONFIG_PMIC_CHILDREN=y +# CONFIG_SPL_PMIC_CHILDREN is not set +# CONFIG_PMIC_ACT8846 is not set +# CONFIG_DM_PMIC_PFUZE100 is not set +# CONFIG_DM_PMIC_MAX77686 is not set +CONFIG_PMIC_RK808=y +# CONFIG_PMIC_S2MPS11 is not set +# CONFIG_DM_PMIC_SANDBOX is not set +# CONFIG_PMIC_S5M8767 is not set +# CONFIG_PMIC_TPS65090 is not set +CONFIG_DM_REGULATOR=y +# CONFIG_SPL_DM_REGULATOR is not set +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK808=y +CONFIG_DM_PWM=y +CONFIG_PWM_ROCKCHIP=y +# CONFIG_PWM_TEGRA is not set +CONFIG_RAM=y +CONFIG_SPL_RAM=y + +# +# Remote Processor drivers +# + +# +# Real Time Clock +# +# CONFIG_DM_RTC is not set + +# +# Serial drivers +# +CONFIG_REQUIRE_SERIAL_CONSOLE=y +CONFIG_SERIAL_PRESENT=y +CONFIG_SPL_SERIAL_PRESENT=y +CONFIG_DEBUG_UART=y +# CONFIG_DEBUG_UART_ALTERA_JTAGUART is not set +# CONFIG_DEBUG_UART_ALTERA_UART is not set +CONFIG_DEBUG_UART_NS16550=y +# CONFIG_DEBUG_UART_S5P is not set +# CONFIG_DEBUG_UART_UARTLITE is not set +# CONFIG_DEBUG_UART_ARM_DCC is not set +# CONFIG_DEBUG_UART_ZYNQ is not set +# CONFIG_DEBUG_UART_PL010 is not set +# CONFIG_DEBUG_UART_PL011 is not set +CONFIG_DEBUG_UART_BASE=0xff690000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +# CONFIG_DEBUG_UART_BOARD_INIT is not set +# CONFIG_DEBUG_UART_ANNOUNCE is not set +# CONFIG_DEBUG_UART_SKIP_INIT is not set +# CONFIG_ALTERA_JTAG_UART is not set +# CONFIG_ALTERA_UART is not set +# CONFIG_FSL_LPUART is not set +CONFIG_SYS_NS16550=y + +# +# Sound support +# +# CONFIG_SOUND is not set + +# +# SPI Support +# +# CONFIG_ALTERA_SPI is not set +# CONFIG_CADENCE_QSPI is not set +# CONFIG_DESIGNWARE_SPI is not set +# CONFIG_EXYNOS_SPI is not set +# CONFIG_FSL_DSPI is not set +# CONFIG_FSL_QSPI is not set +# CONFIG_ICH_SPI is not set +CONFIG_ROCKCHIP_SPI=y +# CONFIG_TEGRA114_SPI is not set +# CONFIG_TEGRA20_SFLASH is not set +# CONFIG_TEGRA20_SLINK is not set +# CONFIG_TEGRA210_QSPI is not set +# CONFIG_XILINX_SPI is not set +# CONFIG_FSL_ESPI is not set +# CONFIG_TI_QSPI is not set +# CONFIG_DM_THERMAL is not set + +# +# Timer Support +# +# CONFIG_TIMER is not set + +# +# TPM support +# +# CONFIG_USB is not set + +# +# Graphics support +# +CONFIG_DM_VIDEO=y +CONFIG_VIDEO_BPP8=y +CONFIG_VIDEO_BPP16=y +CONFIG_VIDEO_BPP32=y +CONFIG_CONSOLE_NORMAL=y +# CONFIG_CONSOLE_ROTATION is not set +# CONFIG_CONSOLE_TRUETYPE is not set + +# +# TrueType Fonts +# +# CONFIG_VIDCONSOLE_AS_LCD is not set +# CONFIG_VIDEO_VESA is not set +# CONFIG_VIDEO_LCD_ANX9804 is not set +# CONFIG_VIDEO_LCD_SSD2828 is not set +# CONFIG_VIDEO_MVEBU is not set +CONFIG_I2C_EDID=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_ROCKCHIP=y +# CONFIG_VIDEO_TEGRA20 is not set +# CONFIG_VIDEO_TEGRA124 is not set +# CONFIG_VIDEO_BRIDGE is not set +# CONFIG_PHYS_TO_BUS is not set + +# +# File systems +# + +# +# Library routines +# +# CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED is not set +CONFIG_HAVE_PRIVATE_LIBGCC=y +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_SYS_HZ=1000 +CONFIG_USE_TINY_PRINTF=y +CONFIG_REGEX=y +# CONFIG_LIB_RAND is not set +CONFIG_CMD_DHRYSTONE=y +CONFIG_RSA=y +CONFIG_RSA_SOFTWARE_EXP=y +# CONFIG_TPM is not set + +# +# Hashing Support +# +# CONFIG_SHA1 is not set +# CONFIG_SHA256 is not set +# CONFIG_SHA_HW_ACCEL is not set + +# +# Compression Support +# +# CONFIG_LZ4 is not set +CONFIG_ERRNO_STR=y +# CONFIG_UNIT_TEST is not set diff --git a/include/configs/chromebook_speedy.h b/include/configs/chromebook_speedy.h new file mode 100644 index 0000000..67f45c0 --- /dev/null +++ b/include/configs/chromebook_speedy.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#include + +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT +#define CONFIG_SPL_SPI_LOAD +#define CONFIG_SPI_FLASH_GIGADEVICE + +#define CONFIG_CMD_SF_TEST +#define CONFIG_CMD_TIME + +#undef CONFIG_SPL_GPIO_SUPPORT + +#define CONFIG_KEYBOARD + +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT + +#define CONFIG_SYS_WHITE_ON_BLACK +#define CONFIG_CONSOLE_SCROLL_LINES 10 + +#endif diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 4424284..cd4d822 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -188,7 +188,7 @@ $(obj)/$(SPL_BIN)-pad.bin: $(obj)/$(SPL_BIN) # pass removes various unused properties from the remaining nodes. # The output is typically a much smaller device tree file. quiet_cmd_fdtgrep = FDTGREP $@ - cmd_fdtgrep = $(objtree)/tools/fdtgrep -b u-boot,dm-pre-reloc -RT $< \ + cmd_fdtgrep = $(objtree)/tools/fdtgrep -b u-boot,dm-pre-reloc -R $< \ -n /chosen -O dtb | \ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) -- 1.9.1